View S524A40X20_8732875.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

s524a40x10/40x20/40x40 1k/2k/4k-bit serial eeprom for low power with software write protect data sheet 2 - 1 overview the s524a40x10/40x20/40x40 serial eeprom has a 1,024/2,048/4,096 - bit (128/256/512 - byte) capacity, supporting the standard i 2 c? - bus serial interface. it is fabricated using samsung?s most advanced cmos technology. it has been developed for low powe r and low voltage applications (1.8 v to 5.5 v). important features are a hardware - based write protection circuit for the entire memory area and software - based write protection logic for the lower 128 bytes. hardware - based write protection is controlled by the state of the write - protect (wp) pin. the software - based method is one - time programmable and permanent. using one - page write mode, you can load up to 16 bytes of data into the eeprom in a single write operation. another significant feature of the s524a 40x10/40x20/40x40 is its support for fast mode and standard mode. features i 2 c - bus interface two - wire serial interface automatic word address increment eeprom 1k/2k/4k - bit (128/256/512 - byte) storage area 16 - byte page buffer typical 3 ms write cycle time with auto - erase function hardware - based write protection for the entire eeprom (using the wp pin) software - based write protection for the lower 128 - byte eeprom eeprom programming voltage generated on chip 1,000,000 erase/write cycles 100 years data retention operating characteristics operating voltage ? 1.8 v to 5.5 v operating current ? maximum write current: < 3 ma at 5.5 v ? maximum read current: < 200 m a at 5.5 v ? maximum stand - by current: < 1 m a at 5.5 v operating temperature range ? ? 25c to + 70c (commercial) ? ? 40c to + 85c (industrial) operating clock frequencies ? 100 khz at standard mode ? 400 khz at fast mode electrostatic discharge (esd) ? 5,000 v (hbm) ? 500 v (mm) packages 8 - pin dip, sop, and tssop
s524a40x10/40x20/40x 40 serial eeprom da ta sheet 2 - 2 start/stop logic slave address comparator word address pointer row decoder eeprom cell array 128 x 8 bits 256 x 8 bits 512 x 8 bits hv generation timing control control logic column decoder data register d out and ack scl wp sda a0 a1 a2 figure 2 - 1. s524a40x10/40x20/40x40 block diagram
data sheet s524a40x 10/40x20/40x40 s erial eeprom 2 - 3 s524a40x10/ 40x20/40x40 v cc wp scl sda a0 a1 a2 v ss note: the s524a40x10/40x20/40x40 is available in 8-pin dip, sop, and tssop package. figure 2 - 2. pin assignment diagram table 2 - 1. s524a40x10/40x20/40x40 pin descriptions name type description circuit type a0, a1, a2 input input pins for device address selection. to configure a device address, these pins should be connected to the v cc or v ss of the device. these pins are internally pulled down to v ss . 1 v ss ? ground pin. ? sda i/o bi - directional data pin for the i 2 c - bu s serial data interface. schmitt trigger input and open - drain output. an external pull - up resistor must be connected to v cc. typical values for this pull - up resistor are 4.7 k w (100 khz) and 1 k w (400 khz). 3 scl input schmitt trigger input pin for serial clock input. 2 wp input input pin for hardware write protection control. if you tie this pin to v cc, the write function is disabled to protect previously written data in the entire memory; if you tie it to v ss , t he write function is enabled. this pin is internally pulled down to v ss . 1 v cc ? single power supply. ? note : see the following page for diagrams of pin circuit types 1, 2, and 3.
s524a40x10/40x20/40x 40 serial eeprom da ta sheet 2 - 4 a0, a1, a2, wp figure 2 - 3. pin circuit type 1 scl noise filter figure 2 - 4. pin circuit type 2 sda v ss data out noise filter data in figure 2 - 5. pin circuit type 3
data sheet s524a40x 10/40x20/40x40 s erial eeprom 2 - 5 function description i 2 c - bus interface the s524a40x10/40x20/40x40 supports the i 2 c - bus serial interface data transmission protocol. the two - wire bus consists of a serial data line (sda) an d a serial clock line (scl). the sda and the scl lines must be connected to v cc by a pull - up resistor that is located somewhere on the bus. any device that puts data onto the bus is defined as the ?transmitter? and any device that gets data from the bus is the ?receiver.? the bus is controlled by a master device which generates the serial clock and start/stop conditions, controlling bus access. using the a0,a1 and a2 input pins, up to eight s524a40x10/40x20 (four for s524a40x40 ) devices can be connected to the s ame i 2 c - bus as slaves (see figure 2 - 6). both the master and slaves can operate as transmitter or receiver, but the master device determines which bus operating mode would be active. sda bus master (transmitter/ receiver) mcu S524A40X20 tx/rx a0 a1 a2 slave 1 to v cc or v ss S524A40X20 tx/rx a0 a1 a2 slave 2 to v cc or v ss S524A40X20 tx/rx a0 a1 a2 slave 3 to v cc or v ss S524A40X20 tx/rx a0 a1 a2 slave 8 to v cc or v ss r v cc r v cc scl note: the a0 does not affect the device address of the s524a40x40. figure 2 - 6. typical configuration (16 kbits of memory on the i 2 c - bus)
s524a40x10/40x20/40x 40 serial eeprom da ta sheet 2 - 6 i 2 c - bus protocols here are several rules for i 2 c - bus transfers: ? a new data transfer can be initiated only when the bus is currently not busy. ? msb is always transferred first in transmitting data. ? during a data transfer, the data line (sda) must remain stable whenever the clock line (scl) is high. the i 2 c - bus interface supports the following communication protocols: bus not busy : the sda and the scl lines remain high level when the bus is not active. start condition : start condition is initiated by a high - to - low transition of the sda line while scl remains high level. all bus commands must be preceded by a start condition. stop condition : a stop condition is initiated by a low - to - high transition of the sda line while sc l remains high level. all bus operations must be completed by a stop condition (see figure 2 - 7). scl sda start condition data or ack valid data change ~ ~ ~ ~ stop condition figure 2 - 7. data transmission sequence data valid : following a start condition, the data becomes valid if the data line remains stable for the duration of the high period of scl. new data must be put onto the bus while scl is low. bus timing is one clock pulse per data bit. the number of data bytes to be transferred is determined by the master device. the total number of bytes that can be transferred in one operation is theoretically unlimited. ack (acknowledge) : an ack signal indicates that a data transfer is completed successfully. the transmitter (the master or the slave) releases the bus after transmitting eight bits. during the 9th clock, which the master generates, the receiver pulls the sda line low to acknowledge that it successfully received the eight bits of data (see figure 2 - 8). but the slave does not send an ack if an internal write cycle is still in progress. in da ta read operations, the slave releases the sda line after transmitting 8 bits of data and then monitors the line for an ack signal during the 9th clock period. if an ack is detected, the slave will continue to transmit data. if an ack is not detected, the slave terminates data transmission and waits for a stop condition to be issued by the master before returning to its stand - by mode.
data sheet s524a40x 10/40x20/40x40 s erial eeprom 2 - 7 master scl line data from transmitter ack ack from receiver bit 9 bit 1 figure 2 - 8. acknowledge response from receiver slave address : after the master initiates a start condition, it must output the address of the device to be accessed. the most significant four bits of the slave address are called the ?device identifier?. the identifier for the s524a40x10/40x20/40x40 is ?1010b?. the next three bits comprise the address of a specific device. the device address is defined by the state of the a0, a1 and a2 pins. using this addressing scheme, you can cascade up to eight s524a40x10/40x20 or four s524a40x40 on the bus (see table 2 - 2 below). the b1 for s524a40x40 is used by the master to select which of the blocks of internal memory (1 block = 256 words) are to be accessed. the bit is in effect the most significant bit of the word address. read/write : the final (eighth) bit of the slave address defines the type of operation to be performed. if the r / w bit is ?1?, a read operation is executed. if it is ?0?, a write operation is executed. table 2 - 2. slave device addressing function device identifier device address r/ w bit b7 b6 b5 b4 b3 b2 b1 (note) b0 read 1 0 1 0 a2 a1 a0 1 write 1 0 1 0 a2 a1 a0 0 write - protect 0 1 1 0 a2 a1 a0 0 note: the b1 for s524a40x40 corresponds to the msb of the memory ar r ay address word .
s524a40x10/40x20/40x 40 serial eeprom da ta sheet 2 - 8 byte write operation in a complete byte write operation, the master transmits the slave address, word address, and one data byte to the s524a40x10/40x20/40x40 slave device (see figure 2 - 9). slave address start word address data stop a c k a c k a c k figure 2 - 9. byte write operation following the start condition, the master sends the device identifier (4 bits), the device ad dress (3 bits), and an r / w bit set to ?0? onto the bus. then the addressed s524a40x10/40x20/40x40 generates an ack and waits for the next byte. the next byte to be transmitted by the master is the word address. this 8 - bit address is written into the word address pointer of the s524a40x10/40x20/40x40. when the s524a40x10/40x20/40x40 receives the word address, it responds by issuing an ack and then waits for the next 8 - bit data. when it receives the data byte, the s524a40x10/40x20/40x40 again responds with a n ack. the master terminates the transfer by generating a stop condition, at which time the s524a40x10/40x20/40x40 begins the internal write cycle. while the internal write cycle is in progress, all s524a40x10/40x20/40x40 inputs are disabled and the s524a40x10/40x20/40x40 does not respond to additional requests from the master.
data sheet s524a40x 10/40x20/40x40 s erial eeprom 2 - 9 page write operation the s524a40x10/40x20/40x40 can also perform 16 - byte page write operation. a page write operation is initiated in the same way as a byte write operation. howeve r, instead of finishing the write operation after the first data byte is transferred, the master can transmit up to 15 additional bytes. the s524a40x10/40x20/40x40 responds with an ack each time it receives a complete byte of data (see figure 2 - 10). slave address word address (n) start a c k a c k data (n) a c k a c k data ( n + 15) stop a c k figure 2 - 10. page write operation the s524a40x10/40x20/40x40 automatically increments the word address pointer each time it receives a complete data byte. when one byte has been received, the internal word address pointer increments to the next address and the next data byte can be received. if the master transmits more than 16 bytes before it generates a stop condition to end the page write operation, the s524a40x10/40x20/40x40 word address pointer value ?rolls over? and the previously received data is overwritten. if the master transmits less than 16 bytes and generates a stop condition, the s524a40x10/40x20/40x40 writes the received data to the corresponding eeprom address. during a page write operation, all inputs are disabled and there is no response to additional requests from the master until the internal write cycle is completed.
s524a40x10/40x20/40x 40 serial eeprom da ta sheet 2 - 10 polling for an ack s ignal when the master issues a stop condition to initiate a write cycle, the s524a40x10/40x20/40x40 starts an internal write cycle. the master can then immediately begin polling for an ack from the slave device. to poll for an ack signal in a write operation, the master issues a start condition followed by the slave address. as long as the s524a40x10/40x20/40x40 remains busy with the write operation, no ack is returned. when the s524a40x10/40x20/40x40 completes the write operation, it returns an ack and the master can then proceed with the next read or write operation (see figure 2 - 11). send write command send stop condition to initiate write cycle send start condition send slave address with r/ w bit = "0" start next operation ack = "0" ? yes no figure 2 - 11. master polling for an ack signal from a slave device
data sheet s524a40x 10/40x20/40x40 s erial eeprom 2 - 11 software - based write protection you can write - protect the lower 128 bytes of the eeprom, locations 00h ? 7fh, in one operation. to do this, you simply write a value to a one - time, write - only register. onc e you have applied this write protection, any write attempt to access the lower 128 - byte area is ignored. in other words, the write protection is permanent. the effect of such a failed attempt is processed in the same way as an invalid i 2 c - bus protocol. to enable write protection, you must execute a write operation to the write protection register. to access the write protection register, you use the device address ?0110?. the word address and data in this write operation can be any value and the timing an d wave form characteristics are identical to a normal byte write operation (see figure 2 - 12). slave address start word address (ignored) stop a c k a c k a c k data (ignored) figure 2 - 12. write protection operation hardware - based write protection you can also write - protect the entire memory area of the s524a40x10/40x20/40x40. this method of write protection is controlled by the state of the write protect (wp) pin. when the wp pin is connected to v cc , any attempt to write a value to the memory is ignored. the s524a40x10/40x20/40x40 will acknowledge slave an d word address, but it will not generate an acknowledge after receiving the first byte of the data. thus the write cycle will not be started when the stop condition is generated. by connecting the wp pin to v ss , t he write function is allowed for the entire memory. these write protection features effectively change the eeprom to a rom in order to prevent data from being overwritten. whenever the write function is disabled, a slave address and a word address are acknowledged on the bus, but data bytes are no t acknowledged.
s524a40x10/40x20/40x 40 serial eeprom da ta sheet 2 - 12 current address byte read operation the internal word address pointer maintains the address of the last word accessed, incremented by one. therefore, if the last access (either read or write) was to the address ?n?, the next read operation would access data at address ?n+1?. when the s524a40x10/40x20/40x40 receives a slave address with the r / w bit set to ?1?, it issues an ack and sends the eight bits of data. the master does not acknowledge the transfer but it does generate a stop conditio n. in this way, the s524a40x10/40x20/40x40 effectively stops the transmission (see figure 2 - 13). slave address data start a c k stop n o a c k figure 2 - 13. current address byte read operation
data sheet s524a40x 10/40x20/40x40 s erial eeprom 2 - 13 random address byte read operation using random read operations, the master can access any memory location at any time. before it issues the slave address with the r / w bit set to ?1?, the master must first perform a ?dummy? write operation. this operation is performed in the following steps: 1. the master first issues a start conditio n, the slave address, and the word address to be read. (this step sets the internal word address pointer of the s524a40x10/40x20/40x40 to the desired address.) 2. when the master receives an ack for the word address, it immediately re - issues a start condition followed by another slave address, with the r / w bit set to ?1?. 3. the s524a40x10/40x20/40x40 then sends an ack and the 8 - bit data stored at the desired address. 4. at this point, the master does not acknowledge the transmission, but generates a sto p condition instead. 5. in response, the s524a40x10/40x20/40x40 stops transmitting data and reverts to its stand - by mode (see figure 2 - 14). slave address word address start a c k a c k slave address a c k n o a c k stop start data (n) figure 2 - 14. random address byte read operation
s524a40x10/40x20/40x 40 serial eeprom da ta sheet 2 - 14 sequential read oper ation sequential read operations can be performed in two ways: as a series of current address reads or as random address reads. the first data is sent in the same way as the previous read mode used on the bus. the next time, however, the master responds with an ack, indica ting that it requires additional data. the s524a40x10/40x20/40x40 continues to output data for each ack it receives. to stop the sequential read operation, the master does not respond with an ack, but instead issues a stop condition. using this method, data is output sequentially with the data from address ?n? followed by the data from ?n+1?. the word address pointer for read operations increments all word addresses, allowing the entire eeprom to be read sequentially in a single operation. after the entir e eeprom is read, the word address pointer ?rolls over? and the s524a40x10/40x20/40x40 continues to transmit data for each ack it receives from the master (see figure 2 - 15). slave address data (n) start a c k a c k n o a c k data (n + x) a c k ~ ~ figure 2 - 15. sequential read operation
data sheet s524a40x 10/40x20/40x40 s erial eeprom 2 - 15 electrical data table 2 - 3. absolute maximum ratings (t a = 25 c) parameter symbol conditions rating unit supply voltage v cc ? ? 0.3 to + 7.0 v input voltage v in ? ? 0.3 to + 7.0 v output voltage v o ? ? 0.3 to + 7.0 v operating temperature t a ? ? 40 to + 85 c storage temperature t stg ? ? 65 to + 150 c electrostatic discharge v esd hbm 5000 v mm 500 table 2 - 4. d.c. electrical characteristics (t a = ? 25 c to + 70 c (c), ? 40 c to + 85 c (i), v cc = 1.8 v to 5.5 v) parameter symbol conditions min typ max unit input low voltage v il scl, sda, a0, a1, a2 ? ? 0.3 v cc v input high voltage v ih 0.7 v cc ? ? v input leakage current i li v in = 0 to v cc ? ? 10 a output leakage current i lo v o = 0 to v cc ? ? 10 a output low voltage v ol i ol = 3 ma, v cc = 2.5 v ? ? 0.4 v supply current write i cc1 v cc = 5.5 v, 400 khz ? ? 3 ma i cc2 v cc = 1.8 v, 100 khz ? ? 1 read i cc3 v cc = 5.5 v, 400 khz ? ? 0.2 i cc4 v cc = 1.8 v, 100 khz ? ? 60 a stand - by current i cc5 v cc = sda = scl = 5.5 v, all other inputs = 0 v ? ? 1 a i cc6 v cc = sda = scl = 1.8 v, all other inputs = 0 v ? ? 1
s524a40x10/40x20/40x 40 serial eeprom da ta sheet 2 - 16 table 2 - 4. d.c. electrical characteristics (continued) (t a = ? 25 c to + 70 c (c), ? 40 c to + 85 c (i), v cc = 1.8 v to 5.5 v) parameter symbol conditions min typ max unit input cap acitance c in 25 c, 1mhz, v cc = 5 v, v in = 0 v, a0, a1, a2, scl and wp pin ? ? 10 pf input/output capacitance c i/o 25 c, 1mhz, v cc = 5 v, v i/o = 0 v, sda pin ? ? 10 table 2 - 5. a.c. electrical characteristics (t a = ? 25 c to + 70 c (c), ? 40 c to + 85 c (i), v cc = 1.8 v to 5.5 v) parameter symbol conditions v cc = 1.8 to 5.5 v (standard mode) v cc = 2.5 to 5.5 v (fast mode) unit min max min max external clock frequency f clk ? 0 100 0 400 khz clock high time t high ? 4 ? 0.6 ? m s clock low time t l ow ? 4.7 ? 1.3 ? rising time t r sda, scl ? 1 ? 0.3 falling time t f sda, scl ? 0.3 ? 0.3 start condition hold time t hd:sta ? 4 ? 0.6 ? start condition setup time t su:sta ? 4.7 ? 0.6 ? data input hold time t hd:dat ? 0 ? 0 ? data input setup time t su:dat ? 0.25 ? 0.1 ? stop condition setup time t su:sto ? 4 ? 0.6 ? bus free time t buf before new transmission 4.7 ? 1.3 ? data output valid from clock low (note) t aa ? 0.3 3.5 ? 0.9 noise spike width t sp ? ? 100 ? 50 ns write cycle time t wr ? ? 5 ? 5 ms note : when acting as a transmitter, the s524a40x10/40x20/40x40 must provide an internal minimum delay time to bridge the undefined period (minimum 300 ns) of the falling edge of scl. this is required to avoid unintended generation of a start or stop condition.
data sheet s524a40x 10/40x20/40x40 s erial eeprom 2 - 17 scl t low t f t r sda in t su:sta t hd:sta t hd:dat t su:dat t su:sto t high sda out t buf t aa figure 2 - 16. timing diagram for bus operations 8th bit wordn scl sda start condition ~ ~ ~ ~ ~ ~ t wr stop condition ack ~ ~ figure 2 - 17. write cycle timing diagram
s524a40x10/40x20/40x 40 serial eeprom da ta sheet 2 - 18 notes

▲Up To Search▲

Price & Availability of S524A40X20

	To Download S524A40X20 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .